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| XC6118 Series Voltage Detector with Separated Sense Pin & Delay Capacitor Pin ETR0213-003 GENERAL DESCRIPTION The XC6118 series is a low power consumption voltage detector with high accuracy detection, manufactured using CMOS process and laser trimming technologies. Since the sense pin is separated from the power supply pin, it allows the IC to monitor the other power supply. The XC6118 can maintain the state of detection even when voltage of the monitored power supply drops to 0V. Moreover, a release delay time can be adjusted by the external capacitor connected to the Cd pin. The VOUT pin is available in both CMOS and N-channel open drain output configurations. APPLICATIONS Microprocessor reset circuitry Charge voltage monitors Memory battery back-up switch circuits Power failure detection circuits FEATURES :2(Detect Voltage1.5V) :30mV(Detect Voltage1.5V) Low Power Consumption : 0.4A(Detect, VIN=1.0V) (TYP.) : 0.8A(Release, VIN=1.0V)(TYP.) Detect Voltage Range : 0.8V5.0V (0.1V increments) Operating Voltage Range : 1.0V6.0V Temperature Characteristics : 100ppm/(TYP.) Output Configuration : CMOS, N-channel open drain Operating Temperature Range : -40+85 Separated Sense Pin : Power supply separation Built-in delay time : Release delay time adjustable Packages : USP-4, SOT-25 High Accuracy TYPICAL APPLICATION CIRCUIT TYPICAL PERFORMANCE CHARACTERISTICS Output Voltage vs. Sense Voltage XC6118C25AGR Ta=25 Output Voltage: VOUT (V) Monitering Power supply 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 0 1 2 3 4 5 6 1.0V 4.0V VIN=6.0V (No Pull-Up resistor needed for CMOS output product) Sense Voltage: VSEN (V) 1/20 XC6118 Series PIN CONFIGURATION Cd/NC 2 5 VSS 3 VSEN 4 VIN VOUT 1 USP-4 BOTTOM VIEW * In the XC6118xxxA/B series, the dissipation pad should not be short-circuited with other pins. * In the XC6118xxxC/D series, when the dissipation pad is short-circuited with other pins, connect it to the NC pin (No.2) pin before use. SOT-25 TOP VIEW PIN ASSIGNMENT PIN NUMBER USP-4 SOT-25 1 2 2 3 4 5 1 5 4 3 2 PIN NAME VOUT Cd NC VSEN VIN VSS FUNCTION Output (Detect "L") Delay Capacitance (*1) No Connection Sense Input Ground (*2) NOTE: *1: With the VSS pin of the USP-4 package, a tab on the backside is used as the pin No.5. *2: In the case of selecting no built-in delay capacitance pin type, the delay capacitance (Cd) pin will be used as the NC. PRODUCT CLASSIFICATION Ordering Information XC6118-(*1) DESIGNATOR DESCRIPTION Output Configuration Detect Voltage SYMBOL C N 08~50 A B Options C D - Packages Taping Type (*2) GR-G MR-G CMOS output N-ch open drain output e.g. 18 1.8V Built-in delay capacitance pin, hysteresis 5% (TYP.)(Standard*) Built-in delay capacitance pin, hysteresis less than 1%(Standard*) No built-in delay capacitance pin, hysteresis 5% (TYP.) (Semi-custom) No built-in delay capacitance pin, hysteresis less than 1% (Semi-custom) USP-4 (Halogen & Antimony free) SOT-25 (Halogen & Antimony free) DESCRIPTION *When delay function isn't used, open the delay capacitance pin before use. (*1) (*2) The "-G" suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant. The device orientation is fixed in its embossed tape pocket. For reverse orientation, please contact your local Torex sales office or representative. (Standard orientation: R-, Reverse orientation: L-) 2/20 XC6118 Series BLOCK DIAGRAMS (1) XC6118CxxA *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118CxxC (semi-custom). (2) XC6118CxxB *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118CxxD (semi-custom). (3) XC6118NxxA *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118NxxC (semi-custom). (4) XC6118NxxB *The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118NxxD (semi-custom). 3/20 XC6118 Series ABSOLUTE MAXIMUM RATINGS XC6118xxxA/B PARAMETER Input Voltage Output Current XC6118C (*1) Output Voltage XC6118N (*2) Sense Pin Voltage Delay Capacitance Pin Voltage Delay Capacitance Pin Current USP-4 Power Dissipation SOT-25 Operating Temperature Range Storage Temperature Range SYMBOL VIN IOUT VOUT VSEN VCD ICD Pd Ta Tstg RATINGS VSS-0.37.0 10 VSS-0.3VIN+0.3 VSS-0.37.0 VSS-0.37.0 VSS-0.3VIN+0.3 5.0 120 250 -40+85 -55+125 Ta=25 UNITS V mA V V V mA mW o o C C XC6118xxxC/D PARAMETER Input Voltage Output Current XC6118C (*1) Output Voltage (*2) XC6118N Sense Pin Voltage USP-4 Power Dissipation SOT-25 Operating Temperature Range Storage Temperature Range NOTE: *1: CMOS output *2: N-ch open drain output Ta=25 SYMBOL VIN IOUT VOUT VSEN Pd Ta Tstg RATINGS VSS-0.37.0 10 VSS-0.3VIN+0.3 VSS-0.37.0 VSS-0.37.0 120 250 -40+85 -55+125 UNITS V mA V V mW o o C C 4/20 XC6118 Series ELECTRICAL CHARACTERISTICS XC6118xxxA PARAMETER Operating Voltage Detect Voltage Hysteresis Width Detect Voltage Line Regulation Supply Current 1 (*2) Ta=25 SYMBOL VIN VDF VHYS VDF/ (VINVDF) ISS1 CONDITIONS VDF(T)=0.85.0V VIN=1.06.0V VIN=1.06.0V VIN=1.06.0V VSEN=VDFx0.9 VIN=1.0V VIN=6.0V VSEN=VDFx1.1 0.4 0.4 0.8 0.9 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 mA 1.0 1.0 1.6 1.8 A A (*1) MIN. 1.0 TYP. MAX. 6.0 UNITS V V V %/V CIRCUITS E-1 E-2 0.1 Supply Current 2 (*2) ISS2 VIN=1.0V VIN=6.0V VSEN=0V, VDS=0.5V(Nch) VIN=1.0V VIN=2.0V IOUT1 Output Current (*3) VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V VSEN=6.0V, VDS=0.5V(Pch) VIN=1.0V VIN=6.0V IOUT2 -0.30 -1.00 -0.08 -0.70 mA Leakage Current CMOS Output ILEAK N-ch Open Drain Output VDF/ (ToprVDF) RSEN RDELAY ICD VTCD VUNS tDF0 tDR0 VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open 0.20 A 0.20 0.40 Temperature Characteristics (*4) -40 CTa85 C VSEN=5.0V VIN=0V VSEN=6.0V VIN=5.0V Cd=0V Cd=0.5V, VIN=1.0V VSEN=6.0V VIN=1.0V VSEN=6.0V VIN=6.0V VIN=VSEN=01.0V VIN=6.0V, VSEN=6.00V Cd: Open VIN=6.0V, VSEN=06.0V Cd: Open 0.4 2.9 1.6 o o 100 ppm/ C o Sense Resistance Delay Resistance E-4 2.0 200 0.5 3.0 0.3 30 30 0.6 3.1 0.4 230 200 2.4 M M A V V s s (*5) Delay capacitance pin Sink Current Delay Capacitance Pin Threshold Voltage Undefined Operation Detect Delay Time (*6) (*7) Release Delay Time (*8) NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: It is calculated from the voltage value of the VIN and the current value of the Cd. *6: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *7: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *8: Delay time from the time of VIN= VDF +VHYS to the time of VOUT = 5.4V when the VSEN rises. 5/20 XC6118 Series ELECTRICAL CHARACTERISTICS (Continued) XC6118xxxB PARAMETER Operating Voltage Detect Voltage Hysteresis Width Detect Voltage Line Regulation Supply Current 1 (*2) Ta=25 SYMBOL VIN VDF VHYS VDF/ (VINVDF) ISS1 CONDITIONS VDF(T)=0.85.0V VIN=1.06.0V VIN=1.06.0V VIN=1.06.0V VSEN=VDFx0.9 VIN=1.0V VIN=6.0V VSEN=VDFx1.1 0.4 0.4 0.8 0.9 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 -0.30 -1.00 0.20 A 0.20 0.40 -0.08 -0.70 mA mA 1.0 1.0 1.6 1.8 A A (*1) MIN. 1.0 TYP. MAX. 6.0 UNITS V V V %/V CIRCUITS E-1 E-3 0.1 Supply Current 2 (*2) ISS2 VIN=1.0V VIN=6.0V VSEN=0V VDS=0.5V(Nch) VIN=1.0V VIN=2.0V IOUT1 Output Current (*3) VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V VSEN=6.0V VDS=0.5V(Pch) IOUT2 CMOS Leakage Current Output N-ch Open Drain Output Temperature Characteristics (*4) (*5) VIN=1.0V VIN=6.0V VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open ILEAK VDF/ (ToprVDF) RSEN RDELAY ICD VTCD VUNS tDF0 tDR0 -40 CTa85 C VSEN=5.0V VIN=0V VSEN=6.0V VIN=5.0V Cd=0V Cd=0.5V, VIN=1.0V VSEN=6.0V VIN=1.0V VSEN=6.0V VIN=6.0V VIN=VSEN=01.0V VIN=6.0V, VSEN=6.00V Cd: Open VIN=6.0V, VSEN=06.0V Cd: Open 0.4 2.9 1.6 o o 100 ppm/ C o Sense Resistance Delay Resistance Sink Current E-4 2.0 200 0.5 3.0 0.3 30 30 0.6 3.1 0.4 230 200 2.4 M M A V V s s Delay capacitance pin Delay Capacitance Pin Threshold Voltage Undefined Operation Detect Delay Time (*6) (*7) Release Delay Time (*8) NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: It is calculated from the voltage value of the VIN and the current value of the Cd. *6: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *7: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *8: Delay time from the time of VIN= VDF +VHYS to the time of VOUT= 5.4V when the VSEN rises. 6/20 XC6118 Series ELECTRICAL CHARACTERISTICS (Continued) XC6118xxxC PARAMETER Operating Voltage Detect Voltage Hysteresis Width Detect Voltage Line Regulation Supply Current 1 (*2) Ta=25 SYMBOL VIN VDF VHYS VDF/ (VINVDF) ISS1 CONDITIONS VDF(T)=0.85.0V VIN=1.06.0V VIN=1.06.0V VIN=1.06.0V VSEN=VDFx0.9 VIN=1.0V VIN=6.0V VSEN=VDFx1.1 0.4 0.4 0.8 0.9 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 -0.30 -1.00 0.20 A 0.20 0.40 -0.08 -0.70 mA mA 1.0 1.0 1.6 1.8 A A (*1) MIN. 1.0 TYP. MAX. 6.0 UNITS V V V %/V CIRCUITS E-1 E-2 0.1 Supply Current 2 (*2) ISS2 VIN=1.0V VIN=6.0V VSEN=0V VDS=0.5V(Nch) VIN=1.0V VIN=2.0V IOUT1 Output Current (*3) VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V VSEN=6.0V VDS=0.5V(Pch) IOUT2 CMOS Leakage Current Output Nch Open Drain Output Temperature Characteristics (*4) (*5) VIN=1.0V VIN=6.0V VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open ILEAK VDF/ (Topr VDF) RSEN VUNS tDF0 tDR0 -40 CTa85 C VSEN=5.0V VIN=0V VIN=VSEN=01.0V VIN=6.0V, VSEN=6.00V VIN=6.0V, VSEN=06.0V o o 100 ppm/ C o Sense Resistance Detect Delay Time E-4 0.3 30 30 0.4 230 200 M V s s Undefined Operation Release Delay Time (*6) (*7) NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *6: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *7: Delay time from the time of VIN= VDF +VHYS to the time of VOUT= 5.4V when the VSEN rises. 7/20 XC6118 Series ELECTRICAL CHARACTERISTICS (Continued) XC6118xxxD PARAMETER Operating Voltage Detect Voltage Hysteresis Width Detect Voltage Line Regulation Supply Current 1 (*2) Ta=25 SYMBOL VIN VDF VHYS VDF/ (VINVDF) ISS1 CONDITIONS VDF(T)=0.85.0V VIN=1.06.0V VIN=1.06.0V VIN=1.06.0V VSEN=VDFx0.9 VIN=1.0V VIN=6.0V VSEN=VDFx1.1 0.4 0.4 0.8 0.9 0.1 0.8 1.2 1.6 1.8 1.9 0.7 1.6 2.0 2.3 2.4 2.5 -0.30 -1.00 0.20 A 0.20 0.40 -0.08 -0.70 mA mA 1.0 1.0 1.6 1.8 A A (*1) MIN. 1.0 TYP. MAX. 6.0 UNITS V V V %/V CIRCUITS E-1 E-3 0.1 Supply Current 2 (*2) ISS2 VIN=1.0V VIN=6.0V VSEN=0V VDS=0.5V(Nch) VIN=1.0V VIN=2.0V IOUT1 Output Current (*3) VIN=3.0V VIN=4.0V VIN=5.0V VIN=6.0V VSEN=6.0V VDS=0.5V(Pch) IOUT2 CMOS Leakage Current Output Nch Open Drain Output Temperature Characteristics (*4) (*5) VIN=1.0V VIN=6.0V VIN=6.0V, VSEN=6.0V, VOUT=6.0V, Cd: Open ILEAK VDF/ (ToprVDF) RSEN VUNS tDF0 tDR0 -40 CTa85 C VSEN=5.0V VIN=0V VIN=VSEN=01.0V VIN=6.0V VSEN=6.00V VIN=6.0V VSEN=06.0V o o 100 ppm/ C o Sense Resistance Detect Delay Time E-4 0.3 30 30 0.4 230 200 M V s s Undefined Operation Release Delay Time (*6) (*7) NOTE: *1: VDF (T): Nominal detect voltage *2: Current to the sense resistor is not included. *3: IOUT2 is applied only to the XC6118C series (CMOS output). *4: It is calculated from the voltage value and the current value of the VSEN. *5: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin. This value is effective only to the XC6118C series (CMOS output). *6: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls. *7: Delay time from the time of VIN= VDF +VHYS to the time of VOUT = 5.4V when the VSEN rises. 8/20 XC6118 Series VOLTAGE CHART SYMBOL PARAMETER NOMINAL VOLTAGE VDF(T) (V) 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 NOTE: *1: When VDF(T)1.4V, the detection accuracy is 30mV. When VDF(T)1.5V, the detection accuracy is 2%. E-1 DETECT VOLTAGE (V) VDF MIN. 0.770 0.870 0.970 1.070 1.170 1.270 1.370 1.470 1.568 1.666 1.764 1.862 1.960 2.058 2.156 2.254 2.352 2.450 2.548 2.646 2.744 2.842 2.940 3.038 3.136 3.234 3.332 3.430 3.528 3.626 3.724 3.822 3.920 4.018 4.116 4.214 4.312 4.410 4.508 4.606 4.704 4.802 4.900 MAX. 0.830 0.930 1.030 1.130 1.230 1.330 1.430 1.530 1.632 1.734 1.836 1.938 2.040 2.142 2.244 2.346 2.448 2.550 2.652 2.754 2.856 2.958 3.060 3.162 3.264 3.366 3.468 3.570 3.672 3.774 3.876 3.978 4.080 4.182 4.284 4.386 4.488 4.590 4.692 4.794 4.896 4.998 5.100 MIN. 0.015 0.017 0.019 0.021 0.023 0.025 0.027 0.029 0.031 0.033 0.035 0.037 0.039 0.041 0.043 0.045 0.047 0.049 0.051 0.053 0.055 0.057 0.059 0.061 0.063 0.065 0.067 0.069 0.071 0.073 0.074 0.076 0.078 0.080 0.082 0.084 0.086 0.088 0.090 0.092 0.094 0.096 0.098 (*1) E-2 HYSTERESIS RANGE (V) VHYS MAX. 0.066 0.074 0.082 0.090 0.098 0.106 0.114 0.122 0.131 0.085 0.147 0.155 0.163 0.171 0.180 0.188 0.196 0.204 0.212 0.220 0.228 0.237 0.245 0.253 0.261 0.269 0.277 0.286 0.294 0.302 0.310 0.318 0.326 0.335 0.343 0.351 0.359 0.367 0.375 0.384 0.392 0.400 0.408 MIN. E-3 HYSTERESIS RANGE (V) VHYS MAX. 0.008 0.009 0.010 0.011 0.012 0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.020 0.021 0.022 0.023 0.024 0.026 0.027 0.028 0.029 0.030 0.031 0.032 0.033 0.034 0.035 0.036 0.037 0.038 0.039 0.040 0.041 0.042 0.043 0.044 0.045 0.046 0.047 0.048 0.049 0.050 0.051 MIN. E-4 SENSE RESISTANCE (M) RSEN TYP. 10 20 0 13 24 15 28 9/20 XC6118 Series TEST CIRCUITS Circuit 1 R=100k Circuit 2 VIN VSEN VOUT XC6118 Series Cd VSS V (No resistor needed for CMOS output products) Circuit 3 Circuit 4 VIN VOUT XC6118 Series Cd VSS A VIN VSEN VSEN VOUT XC6118 Series A Cd VSS Circuit 5 Circuit 6 VIN VSEN VOUT XC6118 Series A Cd VSS Circuit 7 R=100k Circuit 8 VIN VSEN VOUT XC6118 Series V Cd VSS V (No resistor needed for CMOS output products) Circuit 9 R=100k (No resistor needed for CMOS output products) Waveform Measurement Point *No delay capacitance pin available in the XC6118xxxC/D series. 10/20 XC6118 Series OPERATIONAL EXPLANATION A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2. *The XC6118N series (N-ch open drain output) requires a pull-up resistor for pulling up output. Figure 1: Typical application circuit example Sense Pin Voltage: VSEN(MIN.:0V Release Voltage: VDF+VHYS Detect Voltage: VDF MAX.:6.0V) Delay Capacitance Pin Voltage: VCD(MIN.:VSS, MAX.:VIN) Delay Capacitance Pin Threshold Voltage: VTCD Output Voltage Pin Voltage: VOUT (MIN.:VSS MAX:VIN) Figure 2: The timing chart of Figure 1 As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged to the power supply input voltage, (VIN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to reach the detect voltage (VDF) (VSEN>VDF), the output voltage (VOUT) keeps the "High" level (=VIN). * If a pull-up resistor of the XC6118N series (N-ch open drain) is connected to added power supply different from the input voltage pin, the "High" level will be a voltage value where the pull-up resistor is connected. When the sense pin voltage keeps dropping and becomes equal to the detect voltage (VSEN =VDF), an N-ch transistor (M1) for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An inverter (Inv.1) operates as a comparator of the reference voltage VIN, and the output voltage changes into the "Low" level (=VSS). The detect delay time [tDF] is defined as time which ranges from VSEN=VDF to the VOUT of "Low" level (especially, when the Cd pin is not connected: tDF0). While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground voltage (=VSS) level. Then, the output voltage maintains the "Low" level while the sense pin voltage increases again to reach the release voltage (VSEN< VDF +VHYS). 11/20 XC6118 Series OPERATIONAL EXPLANATION (Continued) When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor (M1) for the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay resistor (Rdelay). The inverter (Inv.1) will operate as a comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic Threshold: VTHL=VSS) while the sense pin voltage keeps higher than the detect voltage (VSEN > VDF). While the delay capacitance pin voltage (VCD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC series circuit. Assuming the time to the release delay time (tDR), it can be given by the formula (1). tDR=-RdelayxCdxln(1-VTCD/VIN) ...(1) The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0M(TYP.) and the delay capacitance pin voltage is VIN /2 (TYP.) tDR=RdelayxCdx0.69 ...(2) *Rdelay is 2.0MTYP. As an example, presuming that the delay capacitance is 0.68F, tDR is : 2.0x106x0.68x10-6x0.69=938(ms) * Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the ground (=VSS) level because time described in is short. When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (VCD=VTCD), the inverter (Inv.1) will be inverted. As a result, the output voltage changes into the "High" (=VIN) level. tDR0 is defined as time which ranges from VSEN=VDF+VHYS to the VOUT of "High" level without connecting to the Cd. While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the delay capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the "High"(=VIN) level. Function Chart VSEN Cd TRANSITION OF VOUT CONDITION *1 L H L H L H L H L H L L L H H L H *1: VOUT transits from condition to because of the combination of VSEN and Cd. Example ex. 1) VOUT ranges from `L' to `H' in case of VSEN = `H' (VDRVSEN), Cd='H' (VTCDCd) while VOUT is `L'. ex. 2) VOUT maintains `H' when Cd ranges from `H' to `L', VSEN='H' and Cd='L' when VOUT becomes `H' in ex.1. Release Delay Time Chart DELAY CAPACITANCE [Cd] (F) RELEASE DELAY TIME [tDR] (TYP.) (ms) RELEASE DELAY TIME [tDR] *2 (MIN. ~ MAX.) (ms) 0.010 0.022 0.047 0.100 0.220 0.470 1.000 13.8 30.4 64.9 138 304 649 1380 11.0 ~ 16.6 24.3 ~ 36.4 51.9 ~ 77.8 110 ~ 166 243 ~ 364 519 ~ 778 1100 ~ 1660 * The release delay time values above are calculated by using the formula (2). *2: The release delay time (tDR) is influenced by the delay capacitance Cd. 12/20 XC6118 Series NOTES ON USE 1. Use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage to the device. 2. The power supply input pin voltage drops by the resistance between power supply and the VIN pin, and by through current at operation of the IC. At this time, the operation may be wrong if the power supply input pin voltage falls below the minimum operating voltage range. In CMOS output, for output current, drops in the power supply input pin voltage similarly occur. Moreover, in CMOS output, when the VIN pin and the sense pin are short-circuited and used, oscillation of the circuit may occur if the drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis voltage. Note it especially when you use the IC with the VIN pin connected to a resistor. 3. When the setting voltage is less than 1.0V, be sure to separate the VIN pin and the sense pin, and to apply the voltage over 1.0V to the VIN pin. 4. Note that a rapid and high fluctuation of the power supply input pin voltage may cause a wrong operation. 5. Power supply noise may cause operational function errors, Care must be taken to put the capacitor between VIN-GND and test on the board carefully. 6. When there is a possibility of which the power supply input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operation with the delay capacitance pin (Cd) connected to a capacitor, use a Schottky barrier diode connected between the VIN pin and the Cd pin as the Figure 3 shown below. 7. In N channel open drain output, VOUT voltage at detect and release is determined by resistance of a pull up resistor connected at the VOUT pin. Please choose proper resistance values with refer to Figure 4; During detection: VOUT = VPULL / (1+RPULL / RON) VPULL: Pull up voltage RON(1)On resistance of N channel driver M3 can be calculated as VDS / IOUT1 from electrical characteristics, For example, when (2) RON = 0.5 / 0.8x10-3 = 625MIN.at VIN=2.0V, VPULL = 3.0V and VOUT 0.1V at detect, RPULL= (VPULL /VOUT-1)xRON= (3 / 0.1-1)x62518 In this case, RPULL should be selected higher or equal to 18k in order to keep the output voltage less than 0.1V during detection. (1) RON is bigger when VIN is smaller, be noted. (2) For calculation, Minimum VIN should be chosen among the input voltage range. During releasingVOUT = VPULL / (1 + RPULL / ROFF) VPULLPull up voltage ROFFOn resistance of N channel driver M3 is 15MMIN. when the driver is off (as to VOUT / ILEAK) For examplewhen VPULL = 6.0V and VOUT 5.99V, RPULL = (VPULL / VOUT-1)xROFF = (6/5.99-1)x15x106 25 k In this case, RPULL should be selected smaller or equal to 25 k in order to obtain output voltage higher than 5.99V during releasing. VIN VSEN VOUT R=100k (No resistor needed for CMOS output products) VIN VSEN Cd Cd VSS VOUT NOTEROFF=VOUT/ILEAK Figure 3: Circuit example with the delay capacitance pin (Cd) connected to a Schottky barrier diode Figure 4: Circuit example of XC6118N Series 13/20 XC6118 Series TYPICAL PERFORMANCE CHARACTERISTICS (1) Supply Current vs. Sense Voltage XC6118C25Ax VIN=3.0V 2.0 Supply Current: ISS (A) Ta=85 1.5 25 1.0 0.5 -40 0.0 0 1 2 3 4 5 6 Sense Voltage: VSEN (V) (2) Supply Current vs. Input Voltage XC6118C25Ax VSEN=2.25V XC6118C25Ax VSEN=2.75V 1.2 Supply Current: ISS (A) Supply Current: ISS (A) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 -40 Ta=85 25 Ta=85 1.0 0.8 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 -40 25 Input Voltage: VIN (V) Input Voltage: VIN (V) (3) Detect Voltage vs. Ambient Temperature (4) Detect Voltage vs. Input Voltage XC6118C25Ax VIN=4.0V 2.55 2.55 XC6118C25Ax Detect Voltage: VDF (V) Detect Voltage: VDF (V) Ta=25 85 2.50 2.50 -40 2.45 2.45 -50 -25 0 25 50 75 100 1.0 2.0 3.0 4.0 5.0 6.0 Ambient Temperature: Ta () Input Voltage: VIN (V) 14/20 XC6118 Series TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (5) Hysteresis Voltage vs. Ambient Temperature (6) CD Pin Sink Current vs. Input Voltage XC6118C25Ax VIN=4.0V XC6118C25Ax VSEN=0V VDS=0.5V Hysteresis Voltage: VHYS (V) Cd PIN Current: ICD (mA) 0.20 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 85 25 Ta=-40 0.15 0.10 0.05 -50 -25 0 25 50 75 100 Ambient Temperature: Ta () Input Voltage : VIN (V) (7) Output Voltage vs. Sense Voltage (8) Output Voltage vs. Input Voltage XC6118C25Ax Ta=25 XC6118N25Ax VSEN=VIN Pull-up=VIN R=100k Output Voltage: VOUT (V) 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 0 1 2 3 4 5 6 1.0V 4.0V VIN=6.0V Output Voltage: VOUT (V) 7.0 4.0 3.0 Ta=85 2.0 25 1.0 -40 0.0 -1.0 0 0.5 1 1.5 2 2.5 3 Sense Voltage: VSEN (V) Input Voltage : VIN (V) (9) Output Current vs. Input Voltage XC6118C25Ax VDS(Nch)=0.5V 4.0 0.0 Ta=-40 25 XC6118C25Ax VDS(Pch)=0.5V Output Current: Iout (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 Output Current: Iout (mA) -0.5 Ta=85 -1.0 25 -1.5 -40 85 -2.0 3 4 5 6 0 1 2 3 4 5 6 Input Voltage : VIN (V) Input Voltage : VIN (V) 15/20 XC6118 Series TYPICAL PERFORMANCE CHARACTERISTICS (Continued) (10) Delay Resistance vs. Ambient Temperature (11) Release Delay Time vs. Delay Capacitance XC6118C25Ax 4 3.5 3 2.5 2 1.5 1 -50 XC6118C25Ax Release Delay time: TDR (ms) Ta=25 10000 1000 100 10 1 0.1 0.0001 VIN=1.0V 3.0V 6.0V VSEN=6.0V VCD=0.0V VIN=5.0V Delay Resistance: Rdelay (M) tDR=Cdx2.0x10 6 x0.69 0.001 0.01 0.1 1 -25 0 25 50 75 100 Ambient Temperature: Ta () Delay Capacitor: Cd (F) (12) Detect Delay Time vs. Delay Capacitance (13) Leakage Current vs. Ambient Temperature XC6118N25Ax XC6118C25Ax Ta=25 VIN=VSEN=6.0V VOUT=6.0V Detect Delay time: TDF (s) 1000 4.0V 100 3.0V Leak Current: ILEAK (A) 1 VIN=6.0V 0.25 0.20 10 1.0V 1 0.0001 2.0V 0.15 0.10 -50 -25 0 25 50 75 100 0.001 0.01 0.1 Delay Capacitor: Cd (F) Ambient Temperature: Ta () (14) Leakage Current vs. Supply Voltage XC6118N25Ax VIN=VSEN=6.0V 0.25 Leak Current: ILEAK (A) 0.20 0.15 0.10 0 1 2 3 4 5 6 Output Voltage: VOUT (V) 16/20 XC6118 Series PACKAGING INFORMATION USP-4 SOT-25 +0.2 1.6 -0.1 2.80.2 1.10.1 USP-4 Reference Pattern Layout 1.0 0.35 0.35 4 3 1 0.6 2 USP-4 Reference Metal Mask Design 0.3 1.9 0.3 0.5 1.3MAX 0.2MIN 17/20 XC6118 Series MARKING RULE SOT-25 represents output configuration and integer number of detect voltage CMOS Output (XC6118C Series) MARK VOLTAGE (V) L 0.X M 1.X N 2.X P 3.X R 4.X S 5.X N-ch Open Drain Output (XC6118N Series) MARK T U V X Y Z VOLTAGE (V) 0.X 1.X 2.X 3.X 4.X 5.X 5 4 1 2 SOT-25 3 (TOP VIEW) represents decimal number of detect voltage (ex.) MARK VOLTAGE (V) PRODUCT SERIES 3 0 X.3 X.0 XC6118**3*** XC6118**0*** represents options MARK A B C D OPTIONS Built-in delay capacitance pin with hysteresis 5% (TYP.) (Standard) Built-in delay capacitance pin with hysteresis less than 1% (Standard) No built-in delay capacitance pin with hysteresis 5% (TYP.) (Semi-custom) No built-in delay capacitance pin with hysteresis less than 1% (Semi-custom) PRODUCT SERIES XC6118***A** XC6118***B** XC6118***C** XC6118***D** represents production lot number 0 to 9 A to Z, or inverted characters of 0 to 9, A to Z repeated. (G, I, J, O, Q, and W excluded) *No character inversion used. 18/20 XC6118 Series MARKING RULE (Continued) USP-4 represents output configuration and integer number of detect voltage CMOS Output (XC6118C Series) MARK VOLTAGE (V) L 0.X M 1.X N 2.X P 3.X R 4.X S 5.X N-ch Open Drain Output (XC6118N Series) MARK T U V X Y Z VOLTAGE (V) 0.X 1.X 2.X 3.X 4.X 5.X 1 2 4 3 USP-4 (TOP VIEW) represents decimal number of detect voltage (ex.) MARK 3 0 VOLTAGE (V) X.3 X.0 PRODUCT SERIES XC6118**3*** XC6118**0*** represents options MARK OPTIONS Built-in delay capacitance pin with hysteresis 5% (TYP.) A (Standard) Built-in delay capacitance pin with hysteresis less than 1% B (Standard) No built-in delay capacitance pin with hysteresis 5% (TYP.) C (Semi-custom) No built-in delay capacitance pin with hysteresis less than 1% D (Semi-custom) PRODUCT SERIES XC6118***A** XC6118***B** XC6118***C** XC6118***D** represents production lot number 0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated. (G, I, J, O, Q, and W excluded) *No character inversion used. 19/20 XC6118 Series 1. The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date. 2. We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet. 3. Please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet. 4. The products in this datasheet are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. Atomic energy; aerospace; transport; combustion and associated safety equipment thereof.) 5. Please use the products listed in this datasheet within the specified ranges. Should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. We assume no responsibility for damage or loss due to abnormal use. 7. All rights reserved. No part of this datasheet may be copied or reproduced without the prior permission of TOREX SEMICONDUCTOR LTD. 20/20 |
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